This invention relates to semiconductor devices, and more particularly to pattern sensitivity testing of cell arrays in dynamic memory devices or the like.
Dynamic MOS read/write memory devices have been constructed generally as shown in U.S. Pat. No. 4,081,701 (a 16K dynamic RAM) issued to White, McAdams and Redwine, or U.S. Pat. No. 4,239,993 (a 64K dynamic RAM) issued to McAlexander, White and Rao, both assigned to Texas Instruments. In the manufacture of these devices, exhaustive testing is required; testing equipment and procedures have been developed and are in common use that utilize repeated patterns written into and read from every cell in a device. One such test is for pattern sensitivity; whether or not a given cell is functioning perfectly is not proved by merely writing and reading a 1 then a 0 to this cell, but instead the influence of writing to and reading from adjacent cells must be examined. A device may pass when one test pattern is used but fail another pattern, and thus it is said to be pattern sensitive. A number of different patterns must be run in order to exhaust most of the possibilities. For example, the so-called walking one test involves writing all zeros to the array, then for each bit a zero is read, a 1 is written then read, then a zero is written, etc., requiring at least five read or write accesses for every cell. Many other patterns such as walking one's and zero's, checkerboard, hammer, etc., are used. Some of the patterns require dozens of accesses per cell, some hundreds.
The amount of influence on one cell caused by accessing nearby cells depends upon the array architecture, addressing circuits, substrate resistivity, process variables, and the like. For example, when one cell is accessed, the whole row containing this cell is read and restored. Every cell is read and restored within the refresh time, 2 or 4 ms. A cell array on an epitaxial substrate may have a higher degree of conduction of majority carriers laterally along the substrate, compared to an array on a homogenous substrate. In any event, the spacing along the array, measured in the number of cells, that is sufficient to exclude any reasonable probability of cross-talk between cells is a variable.
The cost of manufacturing a memory device contains as a significant factor the time required on the test machine to run all of the necessary tests. The cost of the silicon chip itself and its package has remained almost constant, or decreased, as the most-common dynamic RAM memory size has progressed through 1K, 4K, b 16K, and 64K bits. Processing and photolithography improvements have made possible the large scale production of 64K-bit devices for the same cost as 4K or 16K devices. However, the time needed on the test machine to run a given set of patterns is necessarily related to the number of bits in the device; when the number of bits is increased by a factor of four, the time needed to run pattern sensitive tests goes up by a factor of four.
Accordingly, in the manufacture of the next generations of dynamic RAMs, i.e., 256K-bit, 1-Megabit, 4-Megabit and beyond, the cost of testing the devices becomes an increasingly large factor.
It is the principal object of this invention to provide improved test methods and circuitry for high density dynamic RAM devices, particularly for pattern sensitivity testing and the like. Another object is to provide testing circuitry for a dynamic RAM or the like in which the testing time is minimized, and the circuitry added to the device is minimized. A further object is to provide high speed test circuitry for semiconductor devices which contain regular arrays of elements such as memory cells, particularly read/write dynamic cells.